Re: Minutes of BTF meeting on July 12th 2004

From: Alec Stanculescu (alec@fintronic.com)
Date: Mon Jul 12 2004 - 14:23:49 PDT

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    Cliff,

    Attributes are data containers associated to specific Verilog
    constructs and are mainly intended to support extensions to the
    language before specific standard constructs are introduced to support
    the given application requiring them.

    Features that are well understood and agreed upon by a large community
    of users should be supported by specialized constructs.

    So, in my opinion attributes are not broken, but are less useful than
    originally thought. They represent merely an extension mechanism that should
    not be used by mature applications.

    Regards,

    Alec

    > Hi, Mac & Steve -
    >
    > I noted from the BTF minutes the following:
    >
    > At 01:10 PM 7/12/2004, Alec Stanculescu wrote:
    >
    > >Alec invited Steve Dovich to present the status of the Encryption
    > >working group. Steve stated that it is waiting for feedback from the
    > >BTF on whether to use formal comments or compiler directive/pragma syntax.
    > >
    > >Karen moved to favor a compiler directive/pragma syntax and Kurt Baty
    > >seconded. All were in favor of this motion and the motion carried.
    > >
    > >Steve Dovich will present to the group a comparison of the advantages
    > >and disadvantages of a specific compiler directive approach vs a
    > >general pragma approach for supporting encryption.
    >
    > In my opinion, this is why I think Verilog-2001 attributes are broken. Note
    > that attributes apparently were not even considered as an option for
    > encryption(???)
    >
    > Also in my opinion, attributes were add to Verilog-2001 to help us move
    > away from comment-pragmas and to a lesser degree, move away from compiler
    > directives.
    >
    > Seems to me that if attributes had been done correctly, we would see
    > domain-specific attributes in popular use by now. This would include
    > attribute-pragmas of the form:
    > (* synthesis, synthesis-stuff *)
    > (* psl, psl-assertion-stuff *)
    > (* encryption, encryption-style-key-whatever *)
    > (* coverage, coverage-directives *)
    > (* placement, asic-placement-info *)
    > etc., etc.
    >
    > For the most part, I don't see anybody rushing to use attributes the way we
    > defined them in Verilog-2001. I can only think of one standardized use of
    > attributes and that is what we defined in the Verilog RTL Synthesis
    > 1364.1-2002 standard, and I have been told that that definition violates
    > actual attribute syntax.
    >
    > In my opinion, we should loosen the restrictions surrounding attribute
    > syntax and just ask the PLI to pick up the attribute string instead of
    > specific attribute values, etc.
    >
    > Regards - Cliff
    >
    >
    > ----------------------------------------------------
    > Cliff Cummings - Sunburst Design, Inc.
    > 14314 SW Allen Blvd., PMB 501, Beaverton, OR 97005
    > Phone: 503-641-8446 / FAX: 503-641-8486
    > cliffc@sunburst-design.com / www.sunburst-design.com
    > Expert Verilog, SystemVerilog, Synthesis and Verification Training
    >
    >

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