RE: Verilog Working Groups

From: Jayaram Bhasker (JBhasker@esilicon.com)
Date: Tue Dec 14 2004 - 11:26:41 PST

  • Next message: Steven J. Dovich: "Review of Encryption proposal scheduled for Wed 12/22 at 1500 UTC"

    Hello Vikash:

     

    Pl contact Tom Fitz (Fitzpatrick, Tom [tom_fitzpatrick@mentorg.com]). He
    is the chair of the 1364 WG. I am sure he will welcome more
    participation.

     

    regards,

    - bhasker

     

      _____

    From: Vikash Rungta [mailto:vrungta@cisco.com]
    Sent: Tuesday, December 14, 2004 2:21 PM
    To: Jayaram Bhasker
    Subject: Verilog Working Groups

     

    Dear Mr. Bhasker,

     

    I am a logic designer at Cisco Systems, San Jose, CA and would like to
    participate in working groups for Verilog standardization committee. Can
    you tell me if you guys meet on a regular basis or there is an active
    mailing list?

     

    Thanx,

    Vikash Rungta

     

    This archive was generated by hypermail 2.1.4 : Tue Dec 14 2004 - 11:12:51 PST and
    sponsored by Boyd Technology, Inc.