From: Steven Sharp (sharp@cadence.com)
Date: Fri Jan 21 2005 - 16:27:54 PST
>What about the command-line input system functions?
>
>I think they would be constant (that is, fixed at elaboration time),
>but since I don't see them mentioned in issue 387
> http://www.boyd.com/1364_btf/report/full_pr/387.html
>it probably can't be resolved now.
I actually did consider them, and decided that they weren't appropriate.
Compiled simulators may allow deferring the setting of these simulation-
time command-line plusargs until simulation time. NC-Verilog does. In
fact, a major use for these system functions is to allow running the
simulation in different ways by using different plusargs, without needing
to recompile the design. You don't want to have to specify your run-time
plusargs at compilation time, or you would have to recompile every time
you wanted to change them.
If you want to use compilation-time command-line arguments to change
how the design elaborates, you can generally use command-line options
to set macro values instead.
Steven Sharp
sharp@cadence.com
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