From: Shalom.Bresticker@freescale.com
Date: Wed Feb 09 2005 - 12:26:04 PST
I take it back, partially.
I just ran a fascinating experiment.
I ran the following simple code:
module m;
integer i;
initial
begin
for (i=0;i<256;i=i+1)
begin
a = i;
$display("s%sa", a);
end
end
endmodule
I urge everyone to try it.
Look at the results on the screen, in your editor, etc.
If you have Unix, try sending the output to cat, vi, textedit, etc.
What appears to happen is simply the obvious:
the Verilog simulator just outputs the required byte (ASCII 0-255) into
the data stream. What it looks like, how it is represented, how it
behaves, that depends on how you view it or process it.
-- Shalom Bresticker Shalom.Bresticker @freescale.com Design & Verification Methodology Tel: +972 9 9522268 Freescale Semiconductor Israel, Ltd. Fax: +972 9 9522890 POB 2208, Herzlia 46120, ISRAEL Cell: +972 50 5441478 [ ]Freescale Internal Use Only [ ]Freescale Confidential Proprietary
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