Re: Query related to escaped character in verilog

From: Steven Sharp (sharp@cadence.com)
Date: Wed Feb 09 2005 - 14:49:09 PST

  • Next message: Steven Sharp: "Re: Query related to escaped character in verilog"

    >module m;
    >integer i;
    >
    >initial
    >begin
    >for (i=0;i<256;i=i+1)
    >begin
    > a = i;
    > $display("s%sa", a);
    >end
    >end
    >
    >endmodule

    I assume you intended to declare "reg [7:0] a;" in there.

    >What appears to happen is simply the obvious:
    >
    >the Verilog simulator just outputs the required byte (ASCII 0-255) into
    >the data stream. What it looks like, how it is represented, how it
    >behaves, that depends on how you view it or process it.

    Well, except for ASCII 0, which gets converted into a space in the output.

    Steven Sharp
    sharp@cadence.com

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