From: Steven Sharp (firstname.lastname@example.org)
Date: Wed Feb 09 2005 - 14:49:09 PST
> a = i;
> $display("s%sa", a);
I assume you intended to declare "reg [7:0] a;" in there.
>What appears to happen is simply the obvious:
>the Verilog simulator just outputs the required byte (ASCII 0-255) into
>the data stream. What it looks like, how it is represented, how it
>behaves, that depends on how you view it or process it.
Well, except for ASCII 0, which gets converted into a space in the output.
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