From: Clifford E. Cummings (email@example.com)
Date: Wed Feb 09 2005 - 15:48:39 PST
Hi, all -
I am probably wasting my time looking at this but it was interesting.
Attached is a uuencoded tar-file with escape-test-code and the outputs from
VCS 7.2 and ModelSim 6.0
Hopefully the uuencoding will preserve all the interesting characters.
Doing a diff (Linux RedHat 7.3) between the tmpout.vcs and tmpout.mti
actually showed a few differences (just a few and none of them are going to
get me upset).
I kind of thought that displaying a null character would not show anything
(VCS did not print a " " but ModelSim did ad from this email thread it
sounds like other simulators are doing the same).
The octal-13 character was also different (line feed or ^M), as were a few
other of the obscure-variety characters.
I don't know if I agree that we should match Verilog-XL if we think it is
doing something wrong. Seems like we cleaned up a couple of Verilog-XL-isms
for IEEE Verilog-1995 and if we think printing a space when a
null-character was requested is wrong, I am inclined to say so. I have not
tried this with C yet. Any takers?
I must admit that I would never base a Verilog-simulator-buying decision on
this, but we should probably clean it up.
No need to send email to me directly. I am on the BTF email list (I was not
sure if Neil was on the list or not).
Regards - Cliff
At 02:49 PM 2/9/2005, Steven Sharp wrote:
> >module m;
> >integer i;
> >for (i=0;i<256;i=i+1)
> > a = i;
> > $display("s%sa", a);
>I assume you intended to declare "reg [7:0] a;" in there.
> >What appears to happen is simply the obvious:
> >the Verilog simulator just outputs the required byte (ASCII 0-255) into
> >the data stream. What it looks like, how it is represented, how it
> >behaves, that depends on how you view it or process it.
>Well, except for ASCII 0, which gets converted into a space in the output.
Cliff Cummings - Sunburst Design, Inc.
14314 SW Allen Blvd., PMB 501, Beaverton, OR 97005
Phone: 503-641-8446 / FAX: 503-641-8486
firstname.lastname@example.org / www.sunburst-design.com
Expert Verilog, SystemVerilog, Synthesis and Verification Training
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