From: Steven Sharp (email@example.com)
Date: Tue Mar 01 2005 - 20:08:26 PST
>I would interpret it as follows...
I just tested this in NC-Verilog. It produces an error if the ports in
different instances of an instance array have different widths. This is
not how I would have interpreted the text, but can be argued. The rules
do refer to "the bit length of the single-instance port", which could be
interpreted as requiring a single consistent bit length for the port in
all the single instances. I interpreted it less strictly.
This archive was generated by hypermail 2.1.4
: Tue Mar 01 2005 - 19:48:44 PST
sponsored by Boyd Technology, Inc.