Re: [sv-bc] potential command line option

From: Steven Sharp (sharp@cadence.com)
Date: Tue Apr 19 2005 - 17:19:19 PDT

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    >I don't have a problem with either of the proposed switches
    >being suggested.

    Neil Korpusik did some investigation and found a variety of tools
    that came uncomfortably close to the proposed switches for configuration
    type files. He suggested putting a 'v' in the option, for 'Verilog',
    which I did in the proposal.

    >Making this change will introduce a double incompatibility issue for
    >vendors that did provide support for 1364-2001 configurations in
    >Verilog source in that such vendors will end up supporting both
    >1364-2001 with the keyword restrictions and 1364-2005 without. Between
    >this and the customer design changes necessary for such a change,
    >we do not believe that removing source support is a good solution.

    It is not clear that this would be a change to what is specified in
    1364-2001. The text doesn't state where configs can appear, and the
    syntax boxes and BNF clearly specify that they cannot appear in Verilog
    source files. This proposal could be viewed as an official interpretation
    with a corresponding clarification in the LRM. There has been no prior
    request for interpretation that would conflict with this. Supporting
    both 1364-2001 and 1364-2005 would not require different behavior.

    Note that specifying that configs _can_ appear in Verilog source
    files would also be a change to the LRM, and would also create
    backwards compatibility issues. It is reasonable to compare the
    relative problems created by each.

    Not allowing configs in source files could create problems for any
    customers relying on such functionality in any existing tools. This
    problem would be restricted to users of those particular tools. It
    would be further restricted to users who were using Verilog configs.
    It would only involve relatively new Verilog code, not older legacy
    code. It would be restricted to users who put configs in the same
    files as Verilog source. Experience with VHDL configurations tends
    to indicate that users don't do that. All of this reduces the users
    who might be impacted to a tiny fraction of Verilog users.

    I would be interested in hearing from any users who are in this
    situation and feel that this is a significant problem. If a vendor
    claims that this is a significant problem for their customers, I
    would expect that they could find a few who would tell us so. I have
    asked this before, and have yet to hear from any.

    Allowing configs in source files could create problems for any users
    using any tools. It could cause problems whether they were using
    configs or not. It could cause problems for legacy Verilog code in
    addition to newer code. Based on tests with our customer design suite,
    around 15% of Verilog designs won't compile with the config keywords
    reserved. It seems clear that this would impact far more users.

    Steven Sharp
    sharp@cadence.com

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