Re: [sv-bc] potential command line option

From: Steven Sharp (sharp@cadence.com)
Date: Wed Apr 20 2005 - 16:13:46 PDT

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    >Just to be fair, I should point out that IEEE rules state that where the
    >standard is ambiguous, an interpretation needs to allow the most liberal
    >interpretation. This is because the content of a standard is determined
    >by what is written there, not by what was intended to be written there,
    >and here there was not even an intent at that time.

    If the meaning of the standard must be determined only by what is written
    there, then configs are clearly not allowed in Verilog source files. This
    is specified unambiguously in the BNF, and there is nothing in the text
    that actually contradicts this.

    Any argument that configs are allowed in Verilog source files could only
    be based on a claim of intent. If such an argument is considered inherently
    invalid, or there was no such intent at the time, then there is nothing to
    support such an interpretation.

    I have not been trying to make this legalistic argument, because I don't
    think this is a practical viewpoint. It is an unfortunate fact that the
    Verilog standard does not completely specify the language. We have to
    rely on additional sources of information, at least for the pre-existing
    parts of the language standardized in 1364-1995. Perhaps a more legalistic
    view should be applied to extensions added later.

    Steven Sharp
    sharp@cadence.com

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