From: Steven Sharp (sharp@cadence.com)
Date: Wed Apr 20 2005 - 18:54:13 PDT
Steve Meyer writes:
> It turns out that "port collapsing on input" is not sufficient to
>model Verilog tran (switch level) gates because a relaxation algorithm
>is needed.
The data terminals of Verilog tran primitives are not inputs. They
are inouts. Inouts are effectively required to be collapsible, so
the extra rule Shalom suggested for switch inputs is not required for
them. Inouts also cannot be connected to constants (or 2-state variables)
so they don't enter into the time-zero constant propagation issue. The
control input of a tranif can be connected to a constant. If so, the
implicit continuous assignment mechanism would trigger it the same way
as any primitive input.
The rules for terminal connections for tran primitives don't require
getting into the details of how tran networks are evaluated. Tran
networks can pass through inout ports of modules and still evaluate
properly, so it is sufficient to regard bidirectional tran terminals
as inouts. It doesn't matter that tools have to do some rather complex
things with the resulting networks to make them evaluate properly. That
is a separable issue.
> Related to this is the time 0 (we call it time minus infinity although
>it really is the delta just before time 0 starts) gate
>evaluation algorithm in Cver not only evaluates constants tied to
>gates and module input ports, but propagates the changes through the
>hierarchy, i.e. evaluate constants connected to gates (and continuous
>assignments), if the gate output connects to a port, treat it as a
>constant port connection and evaluation the strength preserving continuous
>assignment, etc. If the port, connects to a gate elsewhere in the hierarchy,
>treat it as a constant connection, etc.
>
> I think many old bipolar designs required this behavior. It evolved
>since for Cver we needed to match behavior from bug reports.
I can assure you that it is sufficient to treat the original constant
connections as implicit continuous assignments, and evaluate all continuous
assignments that reference constants in the first delta cycle. The rest
of the propagation you describe will happen with normal event simulation.
There may be performance advantages to propagating constants before
simulation starts, because you can then take advantage of knowing that
more values are constant. However, it isn't necessary, and can cause
differences in simulation behavior by changing the order of evaluation.
Steven Sharp
sharp@cadence.com
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