Date: Wed Apr 20 2005 - 20:06:24 PDT
It is a fact that there are others who disagree with this interpretation of
the written words, and it is not explicit.
> If the meaning of the standard must be determined only by what is written
> there, then configs are clearly not allowed in Verilog source files. This
> is specified unambiguously in the BNF, and there is nothing in the text
> that actually contradicts this.
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