RE: FW: New Mantis Issue #667 for V-1364

From: Dave Rich (dave_59@yahoo.com)
Date: Wed Apr 20 2005 - 22:26:20 PDT

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    I agree. Write it up.

    Dave

    --- Steven Sharp <sharp@cadence.com> wrote:
    > Dave Rich wrote:
    > >Evaluating a sequential UDP with an initial statement is exactly
    > like
    > >variable initialization in SystemVerilog. Its output has the initial
    > >value at the start of simulation.
    >
    > But that is exactly what would make it incorrect to evaluate it at
    > time zero. If you evaluate it when there is no edge on an input,
    > and there are no level-sensitive entries that match, then no table
    > entries match and the output goes to X. That would destroy your
    > carefully initialized value. Evaluating a sequential UDP when there
    > was no event at the inputs is a bad idea. Sequential UDP tables are
    > written assuming they will only evaluate when there is an event at
    > an input.
    >
    >
    > >I am thinking of language like:
    > >
    > >All primitives, UDPs, implicit and explicit continuous assignment
    > shall
    > >be evaluated at least once before the end of simulation time 0.
    > Before
    > >time 0 includes during elaboration if all inputs to such constructs
    > are
    > >constant expressions.
    >
    > Primitives and UDPs should be dropped from this. Instead, we should
    > make it clear that anything but a 1-bit net attached to an input
    > terminal will be treated as an implicit continuous assignment, which
    > will take care of them.
    >
    > Steven Sharp
    > sharp@cadence.com
    >
    >

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