RE: [sv-bc] potential command line option

From: Mark Hartoog (Mark.Hartoog@synopsys.com)
Date: Thu Apr 21 2005 - 11:24:09 PDT

  • Next message: Michael McNamara: "RE: [sv-ec] Re: [sv-bc] potential command line option"

    Michael McNamara said:
    >It is apparent here that we have is no ambiguity in the text about
    >where configurations may be included (the standard is self consistant);

    I would disagree that the standard is unambiguous and self consistent.

    As I pointed out in an earlier email the 1364-2001 standard contains
    the following:

    1) configs only appear in library mapping files (BNF)
    2) configs can be cells in logical libraries (1364-2001 13.3.2)
    3) the library map files are NOT source files and must be read before
    any source files are read (1364-2001 13.2.1)
    4) the library mapping in a libmap file applies to source files only
    and therefore not to libmap files (1364-2001 13.2.3).
    5) the config only keywords are included in the list of 'Verilog'
    keywords.

    I don't think this is self consistent. The standard talks of configs
    being cells in libraries, but then provides no mechanism for specifying
    logical libraries for configs.

    Perhaps the intent was that configs could be in some kind of source file
    that the libmaps would apply to. I think Steven Sharp has suggested that
    only the first libmap is not a source file, and that other libmaps could
    be considered source files, but the text is ambiguous about this.

    Mark Hartoog
    700 E. Middlefield Road
    Mountain View, CA 94043
    650 584-5404
    markh@synopsys.com

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