Re: [sv-bc] Keywords

From: Steven Sharp (sharp@cadence.com)
Date: Thu Apr 28 2005 - 17:22:55 PDT

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    Randy Misustin wrote:
    >Hmm...is a change of keywords even something we should put on the table?
    >
    >The good: It preserves the flow and intent of the 2001 configurations
    >while providing a better keyword environment for legacy ()pre-2001) designs.
    >
    >The bad: All vendors and all users of configurations have to make a change.
    >
    >Is it worth a quick straw poll to guage the receptiveness to this kind
    >of thing? I'd especially appreciate hearing from users of configurations.
    >
    >In the interest of getting over what's become a massive hump and
    >achieving consensus, I'd be willing to vote in the affirmative for a
    >keyword change. I'm a little worried about the keyword, "configuration",
    >since I know we have had customers run into this conflict and they must
    >have changed it to something (and "configuration" is a likely
    >candidate!). Other than that, I don't have strong opinions about which
    >keyword.

    I would be willing to vote in favor of it.

    I don't think it would be a big problem for our current users, since we
    could continue to support both keywords in library map files (which is
    the only place we currently support "config"). Then we could add
    support for configurations in Verilog source files using the new safer
    keyword.

    There are some additional technical decisions that would be required:

    1. Choice of keyword. I checked the keywords against another 11 newer
       designs and found one that uses "configuration". There were already
       3 in our suite that used "configure". Also, if we change "config" to
       "configuration", then we really ought to change "endconfig" to
       "endconfiguration". Dennis Brophy's suggestion of "beginconfig" might
       be better.
       
    2. Solution to the "cell" keyword issue. We could go to a context-sensitive
       keyword approach once "config" is fixed, but I would prefer not to do
       that. Alternately, we could change that keyword at the same time. One
       possible alternative is "cellname".
       
    3. Grammar allowed. We could allow the full library map syntax in Verilog
       source files or just configs. If we only allow configs, do we stop
       reserving the library map keywords in Verilog source?

    Steven Sharp
    sharp@cadence.com

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