Configurations Proposal Version 2

From: Clifford E. Cummings (cliffc@sunburst-design.com)
Date: Thu May 05 2005 - 18:28:30 PDT

  • Next message: Neil Korpusik: "Re: [sv-cc] P1364 meeting minutes and email ballot"

    Hi, All -

    I have made a few changes to the configurations proposal based on feedback
    and further research. See the attached file.

    Regards - Cliff

    Changes - 5/5/2005 by Cliff Cummings

    Table of Contents - Added entry for syntax 13-7 cellname

    13.2.1 - "NOTES" to "Library map file details" (per proposal from Tom
    Fitzpatrick - Mantis 658)

    13.1.1 - removed "macromodule" from the proposal (inclusion of "module" in
    the 1364-2001 standard assumes both module and macromodule).

    13.2.1 - added permission for one-line and block comments in Verilog
    library map files (per email from Adam Krolnik - 5/3/2005)

    13.2.1 - added a restriction with examples at the end of this section to
    clarify proper usage of Verilog comments within library files (per email
    from Adam Krolnik - 5/3/2005)

    Syntax 13.2 - | config_declaration
    Already deleted from the BNF - forgot to delete it from this syntax box

    13.2.4 - New Compiler directives in library map files section (per email
    from Adam Krolnik - 5/3/2005)

    13.2.2 - Update to allow the above compiler directives (includes examples
    from Adam Krolnik - 5/3/2005)

    13.2.1.1 - Added a large example with explanation.

    Annex B - required keyword changes

    Index - change index entries for config hierarchical config, cell and
    endconfig

    Adam also mentions two other points that I do not wish to propose changing.
    I believe there is sufficient capabilities in the current definition of
    configurations to cover these points:

    3. If parsers can be forgiving on the need for semicolons, can't we as
    writers of the
    LRM be somewhat forgiving too? I.e. why can't we keep or suggest optional
    semicolons?

    I like the semicolons

    5. It would be nice to exclude a file from being included in a wildcarded
    file_path
    specification. The only way I have seen/used is the following:
    library DONT_USE_THIS_FILE design/my/bad/old/design/files/x_old.v;
    library RTLlib design/...;

    I believe includes and library paths are sufficient to cover this.

    ----------------------------------------------------
    Cliff Cummings - Sunburst Design, Inc.
    14314 SW Allen Blvd., PMB 501, Beaverton, OR 97005
    Phone: 503-641-8446 / FAX: 503-641-8486
    cliffc@sunburst-design.com / www.sunburst-design.com
    Expert Verilog, SystemVerilog, Synthesis and Verification Training


    This archive was generated by hypermail 2.1.4 : Thu May 05 2005 - 18:09:05 PDT and
    sponsored by Boyd Technology, Inc.