Re: Is it a valid testcase

From: Steven Sharp (sharp@cadence.com)
Date: Fri May 13 2005 - 12:26:47 PDT

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    I don't know whether the LRM says anything explicit about this. I
    would expect that only the external name of the port is legal for
    connection

    However, since Verilog-XL seems to allow using the internal name, I
    would also expect many other implementations to follow suit,
    regardless of what the LRM says.

    Steven Sharp
    sharp@cadence.com

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