From: Steven Sharp (firstname.lastname@example.org)
Date: Fri May 13 2005 - 12:26:47 PDT
I don't know whether the LRM says anything explicit about this. I
would expect that only the external name of the port is legal for
However, since Verilog-XL seems to allow using the internal name, I
would also expect many other implementations to follow suit,
regardless of what the LRM says.
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