RE: Is it a valid testcase

From: Kausik Datta (kausikd@cal.interrasystems.com)
Date: Sat May 14 2005 - 11:05:26 PDT

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    Hi Steven,
    The other major simulators like MTI/VCS fail for this testcase.
    Is it possible to make it as a standard via filing an errata for 2005 LRM.
    Considering the increased complexity of System Verilog I think it is better
    to
    Add this clarification in LRM now.
    You can decide in your committee which flow should be accepted.
    Thanks
    Kausik

    -----Original Message-----
    From: Steven Sharp [mailto:sharp@cadence.com]
    Sent: Saturday, May 14, 2005 12:57 AM
    To: etf@boyd.com; btf@boyd.com; kausikd@cal.interrasystems.com
    Subject: Re: Is it a valid testcase

    I don't know whether the LRM says anything explicit about this. I would
    expect that only the external name of the port is legal for connection

    However, since Verilog-XL seems to allow using the internal name, I would
    also expect many other implementations to follow suit, regardless of what
    the LRM says.

    Steven Sharp
    sharp@cadence.com

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