block_item_declaration ::=
         { attribute_instance } block_reg_declaration
       | { attribute_instance } event_declaration
       | { attribute_instance } integer_declaration
       | { attribute_instance } local_parameter_declaration
       | { attribute_instance } parameter_declaration
       | { attribute_instance } real_declaration
       | { attribute_instance } realtime_declaration
       | { attribute_instance } time_declaration
 
     block_reg_declaration ::=
         "reg" [ "signed" ] [ range ] list_of_block_variable_identifiers ";"
 
     list_of_block_variable_identifiers ::=
         block_variable_type { "," block_variable_type }
 
     block_variable_type ::=
         variable_identifier
       | variable_identifier dimension { dimension }

block_item_declaration ::=
    {attribute_instance} "reg" ["signed"] [range] list_of_block_variable_identifiers ";"
  | {attribute_instance} "integer"  list_of_block_variable_identifiers ";"
  | {attribute_instance} "time"     list_of_block_variable_identifiers ";"
  | {attribute_instance} "real"     list_of_block_real_identifiers ";"
  | {attribute_instance} "realtime" list_of_block_real_identifiers ";"
  | {attribute_instance} event_declaration
  | {attribute_instance} local_parameter_declaration
  | {attribute_instance} parameter_declaration

list_of_block_variable_identifiers ::=
    block_variable_type { "," block_variable_type }
  
list_of_block_real_identifiers ::=
    block_real_type     { "," block_real_type }
  
block_variable_type ::= variable_identifier { dimension }
block_real_type ::=     real_identifier     { dimension }

+-----------------------------+------------+--------------------------+
| Expression                  | Bit Length | Comments                 |
+-----------------------------+------------+--------------------------+
| i op j, where op is         |   1        | operands are sized to    |
|   === !== == != > >= < <=   |            | max(L(i), L(j)           |
+-----------------------------+------------+--------------------------+
| i op j, where op is         |   1        | All operands are         |
|   && ||                     |            | self-determined          |
+-----------------------------+------------+--------------------------+

{4{w}} // This is equivalent to {w, w, w, w} 

{   0{1'b0}}  //illegal 
{1'bz{1'b0}}  //illegal 
{1'bx{1'b0}}  //illegal 

   procedural_timing_control_statement ::=
         delay_or_event_control   statement_or_null

   procedural_timing_control_statement ::=
         procedural_timing_control   statement_or_null

library_declaration ::= 
library library_identifier file_path_spec [ { , file_path_spec } ]
    [ -incdir file_path_spec [ { , file_path_spec } ] ;  

TO:

library_declaration ::= 
library library_identifier file_path_spec { , file_path_spec }
    [ -incdir file_path_spec { , file_path_spec } ] ;  

liblist_clause ::= liblist [{library_identifier}]  

TO:

liblist_clause ::= liblist { library_identifier }

escaped_hierarchical_identifier ::= (From Annex A - A.9.3)
  escaped_hierarchical_branch 
    [ { .simple_hierarchical_branch | .escaped_hierarchical_branch } ]

TO:

escaped_hierarchical_identifier ::= (From Annex A - A.9.3)
  escaped_hierarchical_branch 
    { .simple_hierarchical_branch | .escaped_hierarchical_branch }

simple_hierarchical_branch ::=  
          simple_identifier [ [ unsigned_number ] ]  
                [ { .simple_identifier [ [ unsigned_number ] ] } ]  

escaped_hierarchical_branch ::=  
          escaped_identifier [ [ unsigned_number ] ]  
                [ { .escaped_identifier [ [ unsigned_number ] ] } ]  

TO:

simple_hierarchical_branch ::=  
          simple_identifier  [ [ unsigned_number ] ]  
                { .simple_identifier  [ [ unsigned_number ] ] }

escaped_hierarchical_branch ::=  
          escaped_identifier [ [ unsigned_number ] ]  
                { .escaped_identifier [ [ unsigned_number ] ] }

   Expression         Result       Comments
   3**2               9            3*3
   2**3               8            2*2*2, same result as 1<<3
   2**0               1            By definition, and same result as 1<<0
   2**-3'sb1          128          -3'sb1 treated as unsigned 7, same as 1<<-3'sb1
   2.0**-3'sb1        0.5          -3'sb1 coerced to -1.0, giving real reciprocal
   0.0**-1            Undefined    Division by zero is undefined
   9**0.5             3.0          Real square root
   9.0**(1/2)         1.0          Integer division truncates exponent to zero
   -9.0**0.5          Undefined    Square root of negative number is undefined
   -3.0**2.0          9.0          Defined, because real 2.0 is still integral value
   2**(-3'so4/3'so2)  64           Exponent is -3'so2, but is interpreted as 3'o6

In section 12.1.3.2 example 5: 

Change the for loop condition  on the first line after the 
generate <bold generate> from:

 (i=0; i<SIZE+1; i=i+1) to:
 (i=0; i<SIZE; i=i+1)  

On the next line in the comment change:

B1[i].N1[i]  to:
B1[i].N1   

list_of_event_identifiers ::= 
  event_identifier [ dimension { dimension }] 
    { , event_identifier [ dimension { dimension }] } 

list_of_event_identifiers ::= 
  event_identifier { dimension }
    { , event_identifier { dimension } } 

list_of_net_identifiers ::= 
  net_identifier [ dimension { dimension }] 
    { , net_identifier [ dimension { dimension }] } 

list_of_net_identifiers ::= 
  net_identifier { dimension }
    { , net_identifier { dimension } }

reg [31: 0] big_vect;
reg [0 :31] little_vect;
reg [63: 0] dword;
integer sel;

big_vect[ 0 +: 8]    // == big_vect[ 7 : 0]
big_vect[15 -: 8]    // == big_vect[15 : 8]

little_vect[ 0 +: 8] // == little_vect[0 : 7]
little_vect[15 -: 8] // == little_vect[8 :15]

dword[8*sel +: 8]    // variable part-select with fixed width

REPLACE:

port_reference ::= (A.1.4, Syntax 12-1, 12-5)
  port_identifier 
| port_identifier [ constant_expression ] 
| port_identifier [ range_expression ] 

specify_input_terminal_descriptor ::= (A.7.3, Syntax 14-3)
  input_identifier 
| input_identifier [ constant_expression ] 
| input_identifier [ range_expression ]  

specify_output_terminal_descriptor ::= (A.7.3, Syntax 14-3)
  output_identifier 
| output_identifier [ constant_expression ] 
| output_identifier [ range_expression ]  

WITH:
              
port_reference ::= (A.1.4, Syntax 12-1, 12-5)
  port_identifier [ [ constant_range_expression ] ] 

specify_input_terminal_descriptor ::= (A.7.3, Syntax 14-3)
  input_identifier [ [ constant_range_expression ] ] 

specify_output_terminal_descriptor ::= (A.7.3, Syntax 14-3)
  output_identifier [ [ constant_range_expression ] ] 

              The first column should look like this:

              file top.v
              module top();
              adder a1 (...) ;
              adder a2 (...) ;
              endmodule

              The second column should look like this:

              file adder.v
              module adder(...);
              //rtl adder description
              ...
              endmodule

              The third column should look like this:

              file adder.vg
              module adder(...);
              //gate-level adder description
              ...
              endmodule