Precedence: bulk ---------- X-Sun-Data-Type: text X-Sun-Data-Description: text X-Sun-Data-Name: text X-Sun-Charset: us-ascii X-Sun-Content-Lines: 15 x ** -(numbers) some test code and results: included source file "fphdl64_real_functions.inc" included source file "fphdl64_real_functions_base.inc" can be found at: http://www.eda.org/fphdl/ ---------- X-Sun-Data-Type: default X-Sun-Data-Description: default X-Sun-Data-Name: ieee_etf_140_test.v X-Sun-Charset: us-ascii X-Sun-Content-Lines: 29 module ieee_etf_140_test; `include "fphdl64_real_functions.inc" parameter limit = 4; integer x,y,answer; real x_real,answer_real; reg [63:0] x_bits,answer_bits; initial begin x_real = 0.5; x = x_real; $display("x = %0d = x_real =",x,x_real); $display; for(y=limit;y>=-limit;y=y-1) begin for(x=limit;x>=-limit;x=x-1) begin x_real = x; x_bits = $realtobits(x_real); answer_bits = pow(x_bits,y); answer_real = $bitstoreal(answer_bits); answer = answer_real; $display("%0d ** %0d = %0d = ",x,y,answer,answer_real); end end end endmodule ---------- X-Sun-Data-Type: default X-Sun-Data-Description: default X-Sun-Data-Name: verilog.log X-Sun-Charset: us-ascii X-Sun-Content-Lines: 128 Host command: /data/verilog/cadence/LDV_4.0/tools/verilog/bin/verilog.exe Command arguments: ieee_etf_140_test.v VERILOG-XL 4.00.s003 log file created May 5, 2003 13:10:00 VERILOG-XL 4.00.s003 May 5, 2003 13:10:00 Copyright (c) 1995 Cadence Design Systems, Inc. All Rights Reserved. Unpublished -- rights reserved under the copyright laws of the United States. Copyright (c) 1995 UNIX Systems Laboratories, Inc. Reproduced with Permission. THIS SOFTWARE AND ON-LINE DOCUMENTATION CONTAIN CONFIDENTIAL INFORMATION AND TRADE SECRETS OF CADENCE DESIGN SYSTEMS, INC. USE, DISCLOSURE, OR REPRODUCTION IS PROHIBITED WITHOUT THE PRIOR EXPRESS WRITTEN PERMISSION OF CADENCE DESIGN SYSTEMS, INC. RESTRICTED RIGHTS LEGEND Use, duplication, or disclosure by the Government is subject to restrictions as set forth in subparagraph (c)(1)(ii) of the Rights in Technical Data and Computer Software clause at DFARS 252.227-7013 or subparagraphs (c)(1) and (2) of Commercial Computer Software -- Restricted Rights at 48 CFR 52.227-19, as applicable. Cadence Design Systems, Inc. 555 River Oaks Parkway San Jose, California 95134 For technical assistance please contact the Cadence Response Center at 1-877-CDS-4911 or send email to support@cadence.com For more information on Cadence's Verilog-XL product line send email to talkv@cadence.com Compiling source file "ieee_etf_140_test.v" Compiling included source file "fphdl64_real_functions.inc" Compiling included source file "fphdl64_real_functions_base.inc" Continuing compilation of source file "fphdl64_real_functions.inc" Continuing compilation of source file "ieee_etf_140_test.v" Highest level modules: ieee_etf_140_test x = 1 = x_real =0.5 4 ** 4 = 256 = 256 3 ** 4 = 81 = 81.00000000000001 2 ** 4 = 16 = 16 1 ** 4 = 1 = 1 0 ** 4 = 0 = 0 -1 ** 4 = 1 = 1 -2 ** 4 = 16 = 16 -3 ** 4 = 81 = 81.00000000000001 -4 ** 4 = 256 = 256 4 ** 3 = 64 = 64 3 ** 3 = 27 = 27.00000000000001 2 ** 3 = 8 = 8 1 ** 3 = 1 = 1 0 ** 3 = 0 = 0 -1 ** 3 = -1 = -1 -2 ** 3 = -8 = -8 -3 ** 3 = -27 = -27.00000000000001 -4 ** 3 = -64 = -64 4 ** 2 = 16 = 16 3 ** 2 = 9 = 9 2 ** 2 = 4 = 4 1 ** 2 = 1 = 1 0 ** 2 = 0 = 0 -1 ** 2 = 1 = 1 -2 ** 2 = 4 = 4 -3 ** 2 = 9 = 9 -4 ** 2 = 16 = 16 4 ** 1 = 4 = 4 3 ** 1 = 3 = 3 2 ** 1 = 2 = 2 1 ** 1 = 1 = 1 0 ** 1 = 0 = 0 -1 ** 1 = -1 = -1 -2 ** 1 = -2 = -2 -3 ** 1 = -3 = -3 -4 ** 1 = -4 = -4 4 ** 0 = 1 = 1 3 ** 0 = 1 = 1 2 ** 0 = 1 = 1 1 ** 0 = 1 = 1 0 ** 0 = 0 = 0 -1 ** 0 = 1 = 1 -2 ** 0 = 1 = 1 -3 ** 0 = 1 = 1 -4 ** 0 = 1 = 1 4 ** -1 = 0 = 0.25 3 ** -1 = 0 = 0.3333333333333333 2 ** -1 = 1 = 0.5 1 ** -1 = 1 = 1 0 ** -1 = 0 = 0 -1 ** -1 = -1 = -1 -2 ** -1 = -1 = -0.5 -3 ** -1 = 0 = -0.3333333333333333 -4 ** -1 = 0 = -0.25 4 ** -2 = 0 = 0.0625 3 ** -2 = 0 = 0.1111111111111111 2 ** -2 = 0 = 0.25 1 ** -2 = 1 = 1 0 ** -2 = 0 = 0 -1 ** -2 = 1 = 1 -2 ** -2 = 0 = 0.25 -3 ** -2 = 0 = 0.1111111111111111 -4 ** -2 = 0 = 0.0625 4 ** -3 = 0 = 0.015625 3 ** -3 = 0 = 0.03703703703703701 2 ** -3 = 0 = 0.125 1 ** -3 = 1 = 1 0 ** -3 = 0 = 0 -1 ** -3 = -1 = -1 -2 ** -3 = 0 = -0.125 -3 ** -3 = 0 = -0.03703703703703701 -4 ** -3 = 0 = -0.015625 4 ** -4 = 0 = 0.00390625 3 ** -4 = 0 = 0.01234567901234567 2 ** -4 = 0 = 0.0625 1 ** -4 = 1 = 1 0 ** -4 = 0 = 0 -1 ** -4 = 1 = 1 -2 ** -4 = 0 = 0.0625 -3 ** -4 = 0 = 0.01234567901234567 -4 ** -4 = 0 = 0.00390625 0 simulation events (use +profile or +listcounts option to count) CPU time: 0.4 secs to compile + 0.2 secs to link + 0.2 secs in simulation End of VERILOG-XL 4.00.s003 May 5, 2003 13:10:01