From: Steven Sharp (sharp@cadence.com)
Date: Tue Jul 09 2002 - 15:06:13 PDT
Precedence: bulk
The list of reserved words in Annex B includes "include". As far as I know,
the only place that "include" is used as a keyword is in library map files.
It is my understanding that library map files use a separate syntax from
Verilog source files (though the config portions may have the same syntax).
Is there any reason that "include" is listed as a reserved word for Verilog?
There is one possibility that I can think of: if someone chose to use the
name "include" for an instance name, they wouldn't be able to refer to it
in a config in a library map file (or in any other places in the library
map file that might refer to Verilog names). So it could be argued that it
is better to outlaw it in Verilog names completely. It could also be argued
that it is better to maintain backward compatibility as much as possible,
and only make the user change the name if they want to refer to it in a
library map file. Does anyone remember prior discussion of this?
The same arguments apply to "library" and "incdir".
Steven Sharp
sharp@cadence.com
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