From: sharp@cadence.com
Date: Tue Jul 16 2002 - 11:25:09 PDT
Precedence: bulk
>Number: 73
>Category: errata
>Originator: sharp@cadence.com
>Description:
Section 4.1.14 describes the behavior of concatenations when
used in expressions (i.e. rvalues). It also describes
replications as a form of concatenation, and the comments
on the examples give concatenations that they are equivalent
to.
Concatenations are also allowed as lvalues, such as on the
left-hand-side of assignments or attached to output ports.
The statement that replication is equivalent to some
concatenation can be interpreted to mean that replication
is also legal as an lvalue. This was never the intent,
and certainly is not true in Verilog-XL.
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