From: Shalom Bresticker (Shalom.Bresticker@motorola.com)
Date: Wed Jul 24 2002 - 04:20:07 PDT
Precedence: bulk
The following reply was made to PR errata/75; it has been noted by GNATS.
From: Shalom Bresticker <Shalom.Bresticker@motorola.com>
To: btf-bugs@boyd.com
Cc: Krzysztof Kozminski <Krzysztof.A.Kozminski@nsc.com>
Subject: Re: errata/75: Errata to 1364-2001 standard
Date: Wed, 24 Jul 2002 14:13:34 +0300
This is true for procedural assignments as well as continuous assignments.
Stefen,
Please classify this as affecting Section 6, Table 30.
Reword the erratum title as "Table 30 omits nested concatenations".
And it would be nice if you could delete the HTML junk from the detailed
description.
Thanks,
Shalom
Krzysztof Kozminski wrote:
> There is a discrepancy between section A.8.1, and Table 30 in section 6.
>
> According to Section A.8.1, a net_concatenation may contain other
> net_concatenations as its elements, e,g:
>
> { a, b, { C, D} }
>
> is a valid net_concatenation, thus also a valid net_lvalue, and
> therefore it is legal for it to occur on the LHS of a continuous
> assignment.
It also passes Verilog-XL.
> However, Table 30 in section 6 explicitly omits nested
> concatenations from legal LHS of continuous assignment, allowing only
> plain concatenations of nets, bit selects, part selects and indexed
> part selects.
>
> Perhaps the list of valid LHS in Table 30 should be rephrased similarly
> to the language in section 12.3.9.2, which explicitly permits nesting
> of concatenations.
--
Shalom Bresticker Shalom.Bresticker@motorola.com
Design & Reuse Methodology Tel: +972 9 9522268
Motorola Semiconductor Israel, Ltd. Fax: +972 9 9522890
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