From: Steven Sharp (sharp@cadence.com)
Date: Wed Jul 31 2002 - 14:40:10 PDT
Precedence: bulk
>> It is not possible in Verilog to write an explicit event control that is
>> sensitive to an entire array. It would cause implementation problems
>> in some situations.
>
>I'd like to understand this better. I understand that the standard
>currently forbids the concept of being sensitive to an entire array.
>
>But why?
>
>Is it purely for implementation reasons? Or is there a problem with
>the concept itself?
I believe that it is mostly for implementation reasons. However, it
also requires a special extension of the concept of an event control.
>If, given a vector, we can define a change to a vector as a change
>to any bit of the vector, then why can't one define a change to an array
>as a change to any element of the array (and a change to an element of
>the array is defined as a change to any bit of the element).
But we don't define a change to a vector that way. We define a change
to a vector as a change to the value of the expression that consists of
the vector. It is not defined in terms of changes to the subparts of
some object, but in terms of changes to the value of the expression in
the event control.
An event is basically defined as "Evaluate this expression. If that value
changes, then an event has occurred." Note that you can have an event
control like @(a & b != func(c)), which wakes up when that expression
changes value. The definition of an event is based on the concept of the
expression having a value. An entire memory is not an expression with a
value.
This is not just a formalism. Suppose you are waiting on @(vector[j]).
You might think that means you are waiting on the j'th bit of vector to
change. You are not. If that bit changes, but simultaneously the value
of j changes to select a different bit such that the expression vector[j]
still has the same value, then this event control should not wake up. So
events are not defined in terms of parts of objects changing values, they
are defined in terms of expression values. And an event control waiting
on an entire memory can't be defined that way.
Now, we could add a special definition of an event for an entire memory
as happening when there is any change to a word in the memory. But it
would be a special definition, not a direct extension of the existing one.
I don't know whether it would create any actual conflicts. I do know that
it would create implementation problems.
In some situations involving complex expressions (at least in Verilog-XL),
determining whether an event control should wake up requires keeping the
old values of the expressions around and then double-checking whether any
of them have changed value since we executed the event control. Keeping
a copy of the entire contents of a memory around and then checking it
against the current contents to see whether we should wake up or not is
clearly impractical. It might be possible to avoid the need for this, but
it would be difficult without introducing event ordering changes and
possibly extra delta cycles. This could change the behavior of existing
designs.
There may be other implementation issues with this as well, but this is one
that I am aware of.
Steven Sharp
sharp@cadence.com
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