From: Steven Sharp (sharp@cadence.com)
Date: Wed Jul 31 2002 - 21:04:11 PDT
Precedence: bulk
I should clarify the remarks I made about event controls waiting on entire
memories. When I stated that event controls are defined in terms of the
values of expressions, I wasn't referring to an explicit definition in the
standard. The standard only describes named events and value changes on
nets and variables as events. The text doesn't even acknowledge that event
controls waiting on bit selects are allowed, much less the arbitrary
expressions that are actually legal.
I was referring to an implicit definition based on the way Verilog-XL
behaves (the de facto standard). Since I am having to infer that
definition, I should have used a weaker term than "defined", to avoid
misleading anyone.
Steven Sharp
sharp@cadence.com
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