From: Shalom Bresticker (Shalom.Bresticker@motorola.com)
Date: Tue Aug 13 2002 - 06:37:23 PDT
Precedence: bulk
1364 allows me to define a module port in the form
module qq ( .xx(yy) ) ;
where xx will be the port name,
and yy is a signal defined within the module.
In BNF terms, this is
module qq ( .port_identifier(port_reference) ) ;
This is called an "explicit port" in 12.3.2.
My question:
Is it allowed for port_identifier to use the same name as
port_reference?
I.e., module qq ( .yy(yy) ) ;
I can't find something in 1364-1995 or 2001 which forbids it, but if I
try to do it in Verilog-XL, I get
Error! Symbol (yy) previously declared as a port name
[Verilog-SPDPD]
"qq.v", 1:
I am told that NC-Verilog also rejects it, but VCS accepts it.
Looks like we need to add a clarification.
Also, looking at 1364-2001 on this, I found some descriptions which are
not very good:
In 12.1, the second paragraph says,
"The order used used in defining the list of parameters in the
module_parameter_port_list and in the list of ports can be significant
when instantiating the module (see 12.2.2.1 and 12.3.5).The identifiers
in this list shall be declared in input,output,and inout statements
within the module definition. Ports declared in the list of port
declarations shall not be redeclared within the body of the module."
The second sentence I quoted refers to "this list". This is not clear.
It should be "the list of ports".
But anyway, it is not quite accurate, because in the form of port
definition I asked about in the beginning of this mail, the port
identifier is not declared within the module definition.
In the last sentence quoted above, I think "the list of port
declarations" should be "a list_of_port_declarations". Maybe this
sentence is the source of the Cadence behavior.
Similarly, 12.3.3 says, at the beginning,
"Each port_expression in the list of ports for the module declaration
shall also be declared in the body of the module as one of the following
port declarations:input ,output ,or inout (bidirectional)."
Again, this is not quite accurate, as a port_expression can be a
concatenation of identifiers, part-selects and bit-selects. It is not
meant that the expression should be declared.
Comments?
-- Shalom Bresticker Shalom.Bresticker@motorola.com Design & Reuse Methodology Tel: +972 9 9522268 Motorola Semiconductor Israel, Ltd. Fax: +972 9 9522890 POB 2208, Herzlia 46120, ISRAEL Cell: +972 50 441478"The devil is in the details."
This archive was generated by hypermail 2.1.4
: Thu Oct 10 2002 - 09:24:27 PDT
and
sponsored by Boyd Technology, Inc.