From: Steven Sharp (sharp@cadence.com)
Date: Wed Aug 14 2002 - 13:30:02 PDT
Precedence: bulk
The following reply was made to PR errata/84; it has been noted by GNATS.
From: Steven Sharp <sharp@cadence.com>
To: etf-bugs@boyd.com, Shalom.Bresticker@motorola.com
Cc:
Subject: Re: errata/84: Should @* include delay controls?
Date: Wed, 14 Aug 2002 16:23:39 -0400 (EDT)
> > There is no such exception in the standard.
>
> Really? Are you sure?
> I was sure I had read it.
> I don't have it with me to check.
I have the print copy in front of me. Section 9.7.5 is less than a page
long, so it would be hard to miss.
> Not in the general case.
> But there are cases where it is trivial.
It is not as trivial as you think. And how much analysis should a tool do?
You either have to provide a precise algorithm for all tools to use, or a
general statement that tools can eliminate variables from the list if they
can guarantee that they never read a value set by any other process. The
latter would allow for optional optimization, at the cost of differences
in the behavior of different tools.
Of course, if the code is purely combinational, there should be no visible
differences. But I've wasted a lot of time trying to track down race
conditions in designs and trying to explain to customers that the standard
allows different behavior in different simulators in those cases. Stating
in the standard that differences are legal and usually indicate faulty Verilog
code does not mean that those differences don't cause problems.
> E.g.,
> always @*
> begin
> a = b ;
> c = a ;
> end
>
> It is trivial to see that a is always assigned before being used.
And you are incorrect in seeing that. What if a is forced or
quasi-continuous-assigned somewhere else? Then the assignment to a has
no effect and c will be set to the value forced/assigned. Perhaps you
would never do that, but the fact is that a is not guaranteed to be
assigned before being used, even in such a trivial case.
Steven Sharp
sharp@cadence.com
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