From: Clifford E. Cummings (cliffc@sunburst-design.com)
Date: Fri Aug 30 2002 - 13:36:42 PDT
Precedence: bulk
Vassilios and Dennis -
There has been an interesting debate about attribute usage in the 1364.1
Verilog synthesis standard. I don't want to bring you into the debate but
an interesting side note illustrates a point I have been trying to make
about doing a standard twice, once in Accellera and once in the IEEE.
OVI, the Accellera predecessor, developed the OVI Verilog 2.0 Standard in
1993. The OVI standard defined attributes (I did not remember this) but
then Verilog-1995 threw them out of the standard and added them back into
the Verilog-2001 standard in a different form (turned out to be a good
decision, per Steve Sharp).
The IEEE Standardized Verilog-1995 removed or changed many of the OVI 2.0
enhancements. I think the OVI standard was basically considered to be not
worth implementing and everyone chose to implement the IEEE Verilog-1995
Standard instead when it was complete.
What is going to happen to Accellera Verilog credibility if Accellera
implements a SystemVerilog Standard and the IEEE changes it? If the IEEE
changes some of the SystemVerilog functionality, vendors are going to go
back to thinking of Accellera Standards as risky documents to implement
until the IEEE gets done with the enhancements.
I personally think the IEEE is going to adopt the SystemVerilog 3.0
enhancements because for the most part the enhancements have already been
tested and those enhancements that were adopted were the least
controversial and easiest to specify. Right now, I think that Accellera has
regained Verilog-credibility. I think that could change unless Accellera
and the IEEE VSG start working together more closely on a common document.
Food for thought.
Regards - Cliff
At 09:20 PM 8/29/02 -0400, Steven Sharp wrote:
>...
> > Cliff previously wrote:
> >Amusing side note: Cadence (I know, not Steve Sharp) made the attributes
> >proposal for Verilog-2001. We gave Cadence grief for the (* *) syntax and
> >called the tokens the "funny braces." The first time I saw this syntax was
> >before Verilog-2001 efforts when doing mixed Verilog-VHDL simulations with
> >Cadence tools. Cadence tools required the (**) attribute to specify VHDL
> >tool information in the Verilog module header. Every Verilog simulator
> >choked on the attributes except for Cadence simulators. I guess I wasn't
> >too surprised when Cadence proposed (* *) attributes for inclusion in
> >Verilog-2001.
>
>I have an OVI Verilog LRM Version 2.0 dated March 1993 which specifies
>attributes with (* *) syntax. So they were actually standard before
>there was even an IEEE 1364-1995 standard. The OVI version has some
>serious problems that make them impossible to implement fully and way
>too complex. The Cadence tools only implement a subset of the OVI
>attributes. Apparently nobody else even made the effort, or came along
>after the IEEE standard effectively replaced the OVI standard. The
>proposal for the Verilog-2001 attributes is a simplified version that
>is more usable and implementable.
>...
>Steven Sharp
>sharp@cadence.com
----------------------------------------------------
Cliff Cummings - Sunburst Design, Inc.
14314 SW Allen Blvd., PMB 501, Beaverton, OR 97005
Phone: 503-641-8446 / FAX: 503-641-8486
cliffc@sunburst-design.com / www.sunburst-design.com
Expert Verilog, Synthesis and Verification Training
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