From: Steven Sharp (sharp@cadence.com)
Date: Tue Sep 03 2002 - 09:03:38 PDT
Precedence: bulk
Actually, this is legal syntax under the current standard. Making it
some new syntax for declaring a fullcase attribute inside a synthesis
domain would be a substantive change. But it is already a legal way
of setting the synthesis attribute to a string, which could then be
interpreted by a tool as setting various flags. I assumed that was
what Peter meant.
I see several disadvantages of this approach. You couldn't use a macro
to set a flag, since macros are not expanded inside quotes. If you
want to set numerical values instead of just on/off flags, the tool
(possibly a PLI app) would have to do extra work to parse the string
and extract the values. With separate attributes, the Verilog parser
would do that for you. Dealing with constant expressions as values
would be completely impractical. Again, with separate attributes, the
normal attribute mechanism would take care of determining the actual
value for you. Note that constant expressions are useful as attribute
values, since they allow you to propagate values hierarchically via
parameters which are then used to set attributes.
So 1364.1 could use this simple scheme of a single synthesis attribute
set to a string containing all the settings. But it would take away a
lot of the flexibility that the user has in setting things using separate
attributes.
>From: Shalom Bresticker <Shalom.Bresticker@motorola.com>
>
>In IEEE terms, that would be a "substantive change" to IEEE 1364-2001.
>
>FYI
>
>Shalom
>
>
>Peter Flake wrote:
>
>> Could we not consider alternative syntax?
>> (* synthesis = "fullcase, parallelcase", fv = "foo" *)
Steven Sharp
sharp@cadence.com
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