From: Shalom Bresticker (Shalom.Bresticker@motorola.com)
Date: Thu Sep 12 2002 - 08:22:10 PDT
To IEEE 1364 Errata Task Force:
This fellow from Intel submitted to the SystemVerilog committee a review
of the
SystemVerilog LRM.
Much of it is a review of the BNF.
He seems to have found some issues which belong to 1364-2001 rather than
SystemVerilog.
Some of these we have already found, but some appear new.
Worth it to check.
Shalom
-------- Original Message --------
Subject: Fwd: comments and remarks referring to the System-Verilog
3.0LRM
Date: Wed, 11 Sep 2002 14:00:14 -0700
From: Karen Pieper<Karen.Pieper@synopsys.com>
To: <sv-bc@eda.org>
>From: "Jacobi, Dan" <dan.jacobi@intel.com>
>To: Karen.Pieper@synopsys.COM
>Cc: "Maidment, Matthew R" <matthew.r.maidment@intel.com>
>Subject: comments and remarks referring to the System-Verilog 3.0 LRM
>Date: Tue, 10 Sep 2002 09:21:50 +0300
>X-Mailer: Internet Mail Service (5.5.2653.19)
>
>Karen,
>
>My name is Dan Jacobi and I'm a SW Engineer in one of Intel's CAD
>departments.
>Currently I'm working on a parser for the System-Verilog language using the
>"System-Verilog 3.0 Accellera's Extensions to Verilog" publication as my
>reference.
>
>During our work with the RTL Designers in Intel we have came through some
>issues regarding this publication.
>
>All our comments and remarks are documented in the MS word document attached
>to this E-mail.
>
>We are sending you this document as the new SV committee chair-person.
> <<SsytemVerilgo30.ZIP>>
>Thanks,
> Dan Jacobi
>
> Intel Corp.
> Office Tel : (972) - 4 - 8655855
>
>
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