From: Brad Pierce (Brad.Pierce@synopsys.com)
Date: Thu Sep 12 2002 - 16:46:39 PDT
Precedence: bulk
Steven,
The list_of_port_declarations example given in 12.3.4 of the standard is --
module test ( input [7:0] a, input signed b, c, d, output [7:0] e,
output signed reg [7:0] f, g, output signed [7:0] h ) ; body endmodule
However, the output_declaration --
output signed reg [7:0] f, g
is illegal according to the grammar in the standard. According to that
grammar it should be
output reg signed [7:0] f, g
The example in the standard is actually more readable than what I typed
above, because it uses newlines sensibly --
module test ( input [7:0] a,
input signed b, c, d,
output [7:0] e,
output signed reg [7:0] f, g,
output signed [7:0] h ) ;
body
endmodule
An alternative formatting that would better distinguish the different kinds
of commas --
module test ( input [7:0] a
, input signed b, c, d
, output [7:0] e
, output signed reg [7:0] f, g
, output signed [7:0] h
) ;
body
endmodule
-- Brad
-----Original Message-----
From: owner-etf@boyd.com [mailto:owner-etf@boyd.com]On Behalf Of Steven
Sharp
Sent: Thursday, September 12, 2002 2:13 PM
To: etf@boyd.com
Subject: RE: port style parameter declarations
Precedence: bulk
Does the same issue occur with the port declarations as with the parameters?
Steven Sharp
sharp@cadence.com
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