Re: errata/189: 12.1, macromodule needs clarification

From: Brad Pierce (Brad.Pierce@synopsys.com)
Date: Fri Nov 15 2002 - 18:50:20 PST

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    The following reply was made to PR errata/189; it has been noted by GNATS.

    From: "Brad Pierce" <Brad.Pierce@synopsys.com>
    To: <etf-bugs@boyd.com>
    Cc:
    Subject: Re: errata/189: 12.1, macromodule needs clarification
    Date: Fri, 15 Nov 2002 18:42:29 -0800

    >Category: errata
    >Confidential: no
    >Originator: "Brad Pierce" <Brad.Pierce@synopsys.com>
    >Release: 2001b
    >Class: TBD
    >Description:
     In a recent SystemVerilog extension proposal (regarding aliases)
     Kevin Cameron used the "macromodule" construct in an example.
     So apparently it is still considered useful by some experts.
     
     So why not define it properly? At least we could add the
     Verilog-XL restrictions on what may be declared inside of
     macromodules.
     
     -- Brad
     
     
      

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