module foo; vs module foo();

From: Dennis Marsa (drm@xilinx.com)
Date: Tue Nov 19 2002 - 14:28:13 PST

  • Next message: Charles Dawson: "Re: module foo; vs module foo();"

    In yesterday's ETF meeting, there was a brief discussion wrt to
    the semantics of:

       module foo; endmodule

    vs.

       module foo(); endmodule

    I submit that these two modules differ in their number of ports. The
    first has 0 ports, while the second has 1 (unnamed) port, which has no
    size, and no direction.

    This difference can be demonstrated using the VPI as implemented
    by Verilog-XL.

    The attachment contains a testcase which installs a VPI application
    that is called after compilation to dump the ports of each top level
    module of the compiled design.

    Given the following design:

       // This module has 0 ports
       module zero; endmodule

       // This module has 1 port
       module one(); endmodule

       // This module has 2 ports
       module two(,); endmodule

    the following output is generated by the VPI application:

       Compiling source file "port.v"
       Highest level modules:
       zero
       one
       two

       -----------------------------------------
       Module zero
       -----------------------------------------
       Module one
         Port 0 Name=<anonymous> Direction=NoDirection Size=0
       -----------------------------------------
       Module two
         Port 0 Name=<anonymous> Direction=NoDirection Size=0
         Port 1 Name=<anonymous> Direction=NoDirection Size=0
       0 simulation events (use +profile or +listcounts option to count)

    This is consistent with my interpretation of the BNF rules for
    (old-style) port lists. The port list "()" is derived using
    the following sequence of BNF rule applications:

       list_of_ports ==> "(" port { "," port } ")" // BNF rule from section A.1.4
                     ==> "(" port ")" // { "," port } is optional
                     ==> "(" [ port_expression ] ")" // Expand port => [ port_expression ]
                     ==> "(" ")" // port_expression is optional

    Note, this derivation includes one complete expansion of the BNF rule
    "port" which ultimately expands to nothing. Thus, there is one anonymous
    port defined by the port list "()".

    Also note that the new BNF rules for ANSI-style ports
    (e.g. list_of_port_declarations) do not come into play here,
    as Verilog-XL does not support them (at least my copy does not).

    Cheers,

    Dennis

    PS To run the testcase, unpack the attachment, and run "make". You
       may need to adjust the Makefile to point to your Verilog-XL
       installation.

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