errata/204: 12.3.2, port definition names

From: Brad Pierce (Brad.Pierce@synopsys.com)
Date: Wed Nov 20 2002 - 18:13:48 PST

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    >Number: 204
    >Category: errata
    >Originator: "Brad Pierce" <Brad.Pierce@synopsys.com>
    >Environment:
    >Description:

    In section 12.3.2, the last sentence of the first paragraph says --

       "Once a port has been defined, there shall not be another
        port definition with this same name."

    Doesn't this exclude the legal case of --

       module same_name(a,a);
       input a;
       endmodule

    If not, what is the definition of 'port definition'?
    Is it merely the same thing as a port declaration? In that case,
    I guess the sentence is correct, since the following are
    all illegal --

       module same_name2(input a, a);
       endmodule

       module same_name3(input a, input a);
       endmodule

       module same_name4(a,a);
       input a;
       input a;
       endmodule

    But to me the sentence does not suggest the correct idea that
    there is exactly one port declaration per name, but instead
    the incorrect idea that there is exactly one port per name.

    -- Brad

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