Re: errata/20: A.2.8 should prevent all variabledeclarationassignments in named blocks

From: Brad Pierce (Brad.Pierce@synopsys.com)
Date: Thu Nov 21 2002 - 14:00:12 PST

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    The following reply was made to PR errata/20; it has been noted by GNATS.

    From: "Brad Pierce" <Brad.Pierce@synopsys.com>
    To: <etf-bugs@boyd.com>
    Cc:
    Subject: Re: errata/20: A.2.8 should prevent all variabledeclarationassignments in named blocks
    Date: Thu, 21 Nov 2002 13:59:13 -0800

    >Category: errata
    >Confidential: no
    >Originator: "Brad Pierce" <Brad.Pierce@synopsys.com>
    >Release: 2001b
    >Class: TBD
    >Description:
     In my opinion, that's not a strong enough reason.
     If we removed every feature from Verilog that
     could confuse a user, there wouldn't be much left.
     
     -- Brad
     

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