Re: errata/216: 9.5: when is case default executed

From: Brad Pierce (Brad.Pierce@synopsys.com)
Date: Wed Dec 11 2002 - 11:50:00 PST

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    The following reply was made to PR errata/216; it has been noted by GNATS.

    From: "Brad Pierce" <Brad.Pierce@synopsys.com>
    To: <etf-bugs@boyd.com>
    Cc:
    Subject: Re: errata/216: 9.5: when is case default executed
    Date: Wed, 11 Dec 2002 11:47:30 -0800

     The problem seems to be that in the BNF, A "case_item" can be a default
     statement. The first sentence is talking about non-default case items.
     The BNF does not restrict the default to occur at most once, nor to occur
     only at the end.
     
     A C "switch" construct allows at most one "default", but does not require
     that it occur at the end. However, that default will not be followed unless
     none of the cases match. That is, you can put the default as the first
     item instead of the last item in C and it won't change the meaning.
     
     But I've never seen C code that actually puts the default anywhere but at
     the end. It seems like a reasonable restriction. Just because C allows
     something weird doesn't mean Verilog should.
     
        case_statement ::=
              case (expression)
                 case_item {case_item} [case_default_item] endcase
            | ...
     
        case_item ::= expression {, expression } : statement_or_null
     
        case_default_item ::= default [ : ] statement_or_null
     
     Likewise for function_case_statement.
     
     -- Brad
     

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