Re: errata/216: 9.5: when is case default executed

From: Brad Pierce (Brad.Pierce@synopsys.com)
Date: Wed Dec 11 2002 - 12:50:01 PST

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    The following reply was made to PR errata/216; it has been noted by GNATS.

    From: "Brad Pierce" <Brad.Pierce@synopsys.com>
    To: <etf-bugs@boyd.com>
    Cc:
    Subject: Re: errata/216: 9.5: when is case default executed
    Date: Wed, 11 Dec 2002 12:46:53 -0800

     I didn't mean to suggest that the alternative BNF was a correct
     expression of current Verilog syntax. Instead it was intended
     as an example of one possibility for improving Verilog.
     If many Verilog programs already put default statements
     somewhere other than at the end, then such a change
     would break too much existing code. If almost all Verilog
     programs simply put the default at the end, then the traditional
     Verilog syntax might as well be improved.
     
     -- Brad
     
     
     

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