Re: errata/16: Section 19.7: `line - meaning of level parameter is unclear

From: Brad Pierce (Brad.Pierce@synopsys.com)
Date: Fri Dec 13 2002 - 10:50:01 PST

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    The following reply was made to PR errata/16; it has been noted by GNATS.

    From: "Brad Pierce" <Brad.Pierce@synopsys.com>
    To: <etf-bugs@boyd.com>
    Cc:
    Subject: Re: errata/16: Section 19.7: `line - meaning of level parameter is unclear
    Date: Fri, 13 Dec 2002 10:43:41 -0800

     I still don't see why Verilog needs a level field in its `line directive,
     even though CPP doesn't need one in its #line directive. I'm inclined
     to vote against the proposal on the grounds that the level field should
     be eliminated instead.
     
     -- Brad
     
     
     
     
     
     
     

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