From: etf@boyd.com
Date: Mon Dec 16 2002 - 13:11:57 PST
Precedence: bulk
Replace the entire example, including the command line args
and expected output with the following:
Examples:
Given the following Verilog HDL:
`define STRING reg [1024 * 8:0]
module goodtasks;
`STRING str;
integer int;
reg [31:0] vect;
real realvar;
initial
begin
if ($value$plusargs("TEST=%d",int))
$display("value was %d",int);
else
$display("+TEST= not found");
#100 $finish;
end
endmodule
module ieee1354_example;
real frequency;
reg [8*32:1] testname;
reg [64*8:1] pstring;
reg clk;
initial
begin
if ($value$plusargs("TESTNAME=%s",testname))
begin
$display(" TESTNAME= %s.",testname);
$finish;
end
if (!($value$plusargs("FREQ+%0F",frequency)))
frequency = 8.33333; // 166 MHz
$display("frequency = %f",frequency);
pstring = "TEST%d";
if ($value$plusargs(pstring, testname))
$display("Running test number %0d.",testname);
end
endmodule
Adding the following plusarg to the tool's command line:
+TEST=5
will result in the following output:
value was 5
frequency = 8.333330
Adding the following plusarg to the tool's command line:
+TESTNAME=bar
will result in the following output:
+TEST= not found
TESTNAME= bar.
Adding the following plusarg to the tool's command line:
+FREQ+9.234
will result in the following output:
+TEST= not found
frequency = 9.234000
Adding the following plusarg to the tool's command line:
+TEST23
will result in the following output:
+TEST= not found
frequency = 8.333330
Running test number 23.
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