Re: errata/93: PROPOSAL - Section 17.10.2 errors in the example

From: Charles Dawson (chas@cadence.com)
Date: Mon Dec 16 2002 - 13:47:23 PST

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    Precedence: bulk

    A good point that I did not think of. The LRM does not specify
    what should be returned if a conversion fails. Currently
    NC-Verilog produces an error in this case and returns 0 from
    the system function. This may not be correct because the last
    sentence in the first paragraph of section 17.10.2 says:

      No warnings shall be generated when the function returns
      zero (0).

    Obviously, whoever wrote this section did not consider the
    possibility that a conversion would fail. The best solution
    would be to specify another non-zero return code for a
    conversion failure. That would however, require that people
    use the system function in conjunction with a case statement.

      -Chas

    Gordon Vreugdenhil wrote:
    >
    > Precedence: bulk
    >
    > I disagree with the expected output.
    >
    > The matching rules at the beginning of the LRM talk about the
    > return value being non-zero if the "string" is found -- it says
    > nothing about a zero value if the string is found and there
    > is a conversion error.
    >
    > The provided output makes that assumption.
    >
    > The example run with "+TEST=5" should produce:
    >
    > value was 5
    > frequency = 8.333330
    > Running test number x.
    >
    > since the string "TEST" is found and it is only
    > the conversion that fails.
    >
    > If we want to differentiate between a string search
    > failure and a conversion failure, we should specify
    > additional status codes.
    >
    > Gord.
    >
    > etf@boyd.com wrote:
    > >
    > > Precedence: bulk
    > >
    > > Replace the entire example, including the command line args
    > > and expected output with the following:
    > >
    > > Examples:
    > >
    > > Given the following Verilog HDL:
    > >
    > > `define STRING reg [1024 * 8:0]
    > >
    > > module goodtasks;
    > > `STRING str;
    > > integer int;
    > > reg [31:0] vect;
    > > real realvar;
    > >
    > > initial
    > > begin
    > > if ($value$plusargs("TEST=%d",int))
    > > $display("value was %d",int);
    > > else
    > > $display("+TEST= not found");
    > > #100 $finish;
    > > end
    > >
    > > endmodule
    > >
    > > module ieee1354_example;
    > > real frequency;
    > > reg [8*32:1] testname;
    > > reg [64*8:1] pstring;
    > > reg clk;
    > >
    > > initial
    > > begin
    > > if ($value$plusargs("TESTNAME=%s",testname))
    > > begin
    > > $display(" TESTNAME= %s.",testname);
    > > $finish;
    > > end
    > >
    > > if (!($value$plusargs("FREQ+%0F",frequency)))
    > > frequency = 8.33333; // 166 MHz
    > > $display("frequency = %f",frequency);
    > >
    > > pstring = "TEST%d";
    > > if ($value$plusargs(pstring, testname))
    > > $display("Running test number %0d.",testname);
    > > end
    > >
    > > endmodule
    > >
    > > Adding the following plusarg to the tool's command line:
    > >
    > > +TEST=5
    > >
    > > will result in the following output:
    > >
    > > value was 5
    > > frequency = 8.333330
    > >
    > > Adding the following plusarg to the tool's command line:
    > >
    > > +TESTNAME=bar
    > >
    > > will result in the following output:
    > >
    > > +TEST= not found
    > > TESTNAME= bar.
    > >
    > > Adding the following plusarg to the tool's command line:
    > >
    > > +FREQ+9.234
    > >
    > > will result in the following output:
    > >
    > > +TEST= not found
    > > frequency = 9.234000
    > >
    > > Adding the following plusarg to the tool's command line:
    > >
    > > +TEST23
    > >
    > > will result in the following output:
    > >
    > > +TEST= not found
    > > frequency = 8.333330
    > > Running test number 23.
    > >
    > > http://boydtechinc.com/cgi-bin/issueproposal.pl?cmd=view&pr=93
    >
    > --
    > ----------------------------------------------------------------------
    > Gord Vreugdenhil gvreugde@synopsys.com
    > Staff Engineer, VCS (Verification Tech. Group) (503) 547-6054
    > Synopsys Inc., Beaverton OR 

    -- 
Charles Dawson
Senior Engineering Manager
NC-Verilog Team
Cadence Design Systems, Inc.
270 Billerica Road
Chelmsford, MA  01824
(978) 262 - 6273
chas@cadence.com

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