errata/195: PROPOSAL - 3.11.3: last example has syntax errors

From: stefen@boyd.com
Date: Fri Jan 10 2003 - 09:53:54 PST

  • Next message: Dennis Marsa: "Re: errata/20: PROPOSAL - A.2.8 should prevent all variable declarationassignments in named blocks"

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    Change

       module RAM16GEN (DOUT, DIN, ADR, WE, CE)

    to

       module RAM16GEN (output DOUT, input DIN, ADR, WE, CE) ;

    ======================================
    Alternate (friendly amendment?) - James Markevitch

    REPLACE:

       module RAM16GEN (DOUT, DIN, ADR, WE, CE)

    WITH:

       module RAM16GEN (output [7:0] DOUT, input [7:0] DIN,
                        input [5:0] ADR, input WE, CE) ;

    http://boydtechinc.com/cgi-bin/issueproposal.pl?cmd=view&pr=195

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