errata/255: clarify explicitly whether a module may instantiate itself

From: Shalom.Bresticker@motorola.com
Date: Sun Jan 12 2003 - 00:11:40 PST

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    >Number: 255
    >Category: errata
    >Originator: Shalom.Bresticker@motorola.com
    >Environment:
    http://www.eda.org/vlog-synth/hm/0403.html
    >Description:

    Can a module instantiate itself, directly or indirectly?

    Using generates or configurations, it is easy to invent
    useful examples.

    The LRM should answer this question explicitly.

    See the discussion in the thread beginning at
    http://www.eda.org/vlog-synth/hm/0403.html

    It seems to me that even in Verilog-1995, it could have been
    done in Verilog-XL using the `uselib compiler directive to
    make an instance different from its father.

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