errata/259: 19.3.1: Allow escaped identifiers as text macro names

From: Shalom.Bresticker@motorola.com
Date: Sun Jan 12 2003 - 01:13:57 PST

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    >Number: 259
    >Category: errata
    >Originator: Shalom.Bresticker@motorola.com
    >Environment:

    >Description:

    In 19.3.1: In Syntax 19-2 and para. 9,
    and in 19.4, para. 6, and in A.9.3,
    it says that text macro identifiers must be
    simple_identifiers, excluding escaped_identifiers.

    This is the only place in the LRM where simple identifiers
    are allowed and escaped identifiers are not, and I see that
    Verilog-XL allows escaped text macro names as well,
    so I propose to relax that restriction (which I foolishly
    added into the LRM), and allow any identifier to be a
    text macro name.

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