Re: errata/237: A.7.5.3: scalar_timing_check_expressions has redundancies

From: Shalom.Bresticker@motorola.com
Date: Thu Jan 16 2003 - 02:00:00 PST

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    The following reply was made to PR errata/237; it has been noted by GNATS.

    From: Shalom.Bresticker@motorola.com
    To: Brad Pierce <Brad.Pierce@synopsys.com>
    Cc: etf-bugs@boyd.com
    Subject: Re: errata/237: A.7.5.3: scalar_timing_check_expressions has
     redundancies
    Date: Thu, 16 Jan 2003 11:58:54 +0200 (IST)

    > Before proceeding further with this issue, I think we need to resolve
    > the following question --
    >
    > Can timing checks (15.6) really use arbitrary expressions as
    > the BNF suggests, or was the intent to limit them to using
    > primaries (or constant_primaries or ...) ?
     
     I found an old mail from Ted Elkind from 1997-07-31 which may shed some light on
     this. The excerpt starts in the middle of a reply to a previous mail:
     
     start excerpt:
    > timing_check_condition ::=
    > scalar_expression
    >
    >This supports the apparent intent of the actual syntax, and it
    >allows all the examples given in section 14.5.11.
    >
    >(Note: Perhaps the syntax given in 14.5.11 is intended more as a
    >suggested usage pattern than as a linguistic definition.)
     
     I have an older version of the Verilog-XL reference manual that
     explicitly defines scalar_expression. Here's the whole definition
     from Appendix A of the March 1991 version 1.6 manual:
     
          <timing_check_condition>
               ::= <SCALAR_EXPRESSION>
               ||= ~<SCALAR_EXPRESSION>
               ||= <SCALAR_EXPRESSION> == <scalar_constant>
               ||= <SCALAR_EXPRESSION> === <scalar_constant>
               ||= <SCALAR_EXPRESSION> != <scalar_constant>
               ||= <SCALAR_EXPRESSION> !== <scalar_constant>
     
          <SCALAR_EXPRESSION> is a one bit net or a bit select of an
          expanded vector net.
     
     This means that section 14.5.11 incompletely captured what was in the
     Verilof-XL manual, and that the syntax in Annex A incorrectly
     captured what was in section 14.5.11.
     
     It has been a very common Verilog-XL enhancement request to allow
     generalized expressions in timing check conditions. We may want to do
     this for the 1364 standard, but by conscious decision rather than by
     accident.
     
     end excerpt:
     
     Shalom
     

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