SystemVerilog non-donation to IEEE

From: Shalom.Bresticker@motorola.com
Date: Sat Jan 18 2003 - 10:43:23 PST

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    FYI

    ---------- Forwarded message ----------
    Date: Fri, 17 Jan 2003 06:48:56 -0800
    From: Stan Krolikoski <stank@cadence.com>

    Shalom,

    As it turns out, at the Board meeting there was a long discussion about
    when/how SystemVerilog would be donated to the 1364 committee. At the
    end of the discussion, I put forth the motion:

    "The Accellera Board of Directors hereby recognizes that SystemVerilog
    is intended to be an extension to the IEEE Verilog 1364-2001 language
    and instructs the Technical Chair to immediately prepare a donation to
    the IEEE consisting of the
    stable content of SystemVerilog 3.0. Ongoing Accellera SystemVerilog
    committee activities should be structured such that manageable,
    incremental donations to IEEE 1364 are made periodically and
    frequently."

    This was defeated 6-4-1. Motorola, Cadence Verisity and TransEDA voted
    for this proposal. NEC abstained.

    One problem I see is that a lot of the reps on the Accellera board don't
    see much/any value in the IEEE, but really have started to see Accellera
    as a prime standards body on its own. Indeed, the slide in which you
    were quoted was from the portion of Vassilios' presentation where he
    directly contrasted the IEEE's shortcomings against "Accellera's
    strengths". Interestingly enough, later in Vassilios' presentation
    there was a question as to whether Rosetta should move a "a more
    academic forum such as IEEE".

    From my standpoint (and I represent Cadence on this), Accellera' main
    purpose is to accelerate IEEE by incubating them. Standards, especially
    those that have not existed before, often have difficulty getting
    traction in the (rightfully) laborious structure of the IEEE. Thus,
    Accellera can serve as a useful forum in which the rules are somewhat
    more flexible. This added flexibility can be put to good use to produce
    candidate standards, which can be then be strengthened and fully
    codified by the relevant IEEE group. Indeed, Accellera is not the only
    such organization with this mission. I consider OSCI to play the same
    role wrt SystemC. SystemC will go to the IEEE this quarter after a
    period of incubation. Future versions/libraries built around it will be
    pipelined to the IEEE as they become available.

    Unfortunately, I think this view of Accellera is not held by the
    majority of its board. Within this majority the IEEE seen as a slow
    moving group that will eventually be given the SystemVerilog body of
    work once it is "ready", whenever that occurs.

    Stan

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