Re: [Fwd: evaluation order question]

From: Steven Sharp (sharp@cadence.com)
Date: Mon Jan 20 2003 - 11:19:48 PST

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    >When there IS an intra-assignment timing control, why is the
    >variable_lvalue evaluated "at the time specified by the ... timing
    >control" for blocking assignments (9.2.1), but "at the same time as the
    >expression on the right-hand side" for nonblocking assignments (9.2.2)?

    I don't know the historical reasons, and it may have been an accident of
    implementation. I have verified that Verilog-XL actually does this (and
    therefore, so does NC-Verilog and presumably other simulators).

    Steven Sharp
    sharp@cadence.com

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