errata/133: PROPOSAL - Table 12: Precedence rules for operators

From: stefen@boyd.com
Date: Mon Jan 27 2003 - 09:55:24 PST

  • Next message: etf@boyd.com: "errata/181: PROPOSAL - 4.3, 9.2.1-3, A.8.4-5: 12 productions better expressed with 3"

    Precedence: bulk

    Change subclause name
    FROM: "Binary operator precedence"
    TO : "Operator precedence".

    Change the first paragraph
    FROM:
    "The precedence order of binary operators and the
    conditional operator (?:) is shown in Table 12.
    The Verilog HDL has two equality operators.
    They are discussed in 4.1.8."

    TO:
    "The precedence order of the Verilog operators
    is shown in Table 12."

    Change Table 12 as follows:

    Change top row
    FROM: "+ - ! ~ (unary)"
    TO : "Unary + - ! ~ & ~& | ~| ^ ~^ ^~"

    Change rows 8-10
    FROM:
    & ~&
    ^ ^~ ~^
    | ~|

    TO:
    & (binary)
    ^ ^~ ~^ (binary)
    | (binary)

    In last row (conditional operator), delete "Lowest precedence".

    Add new row at bottom: "{} {{}} Lowest precedence".

    REMOVE: last line of Table-10 and last line of Table-9
              and Section 4.1.15

    http://boydtechinc.com/cgi-bin/issueproposal.pl?cmd=view&pr=133

    This archive was generated by hypermail 2.1.4 : Mon Jan 27 2003 - 09:55:45 PST and
    sponsored by Boyd Technology, Inc.