From: Steven Sharp (email@example.com)
Date: Tue Feb 11 2003 - 13:09:02 PST
I asked someone familiar with these in Verilog-XL and got this response:
>Is this reasonable? I don't know much about macromodules.
> "The keyword 'macromodule' can be used interchangeably with
> the keyword 'module'. An implementation may choose to merge
> definitions that use the 'macromodule' keyword with the
> definitions of modules that instantiate them instead of creating
> another level of hierarchy."
Well, the one part that I sort of disagree with is that I'm not sure
that "interchangeably" is really the right word in the first sentence.
To me, interchangeably implies equivalence.
(I know they probably mean lexically interchangeable, but it
would sound funny to say, for example, 'trior' and 'triand'
can be used interchangeably).
Anyway, modules and macromodules are not exactly functionally
equivalent in Verilog-XL because there are special (and well-defined)
names generated for the elements of a macromodule that are
expanded within the instantiating module.
Anyway, I would tend to think that something like this might be better:
The keyword 'macromodule' can be used in place of the keyword
'module' to define a module.
Although the new definition is (also) vague enough that it probably
covers things, it might be possibly be kind of helpful to have
specific language about the naming differences. For what it's worth,
I might have described them more like this:
An implementation may choose to inline the contents of modules
that are declared with the 'macromodule' keyword within the
modules which instantiate them. In such cases, the naming convention
used to reference elements within instantiated macromodules may
differ from that used to reference elements within instantiated
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