From: Shalom.Bresticker@motorola.com
Date: Sat Feb 15 2003 - 09:40:01 PST
Precedence: bulk
The following reply was made to PR errata/189; it has been noted by GNATS.
From: Shalom.Bresticker@motorola.com
To: brad.pierce@synopsys.com
Cc: etf-bugs@boyd.com
Subject: Re: errata/189: PROPOSAL - 12.1, macromodule needs clarification
Date: Sat, 15 Feb 2003 19:38:36 +0200 (IST)
It is yet more complicated than that.
For example, Verilog-XL does not "inline" every macromodule, only macromodules
which obey certain restrictions.
Frankly, since any implementation-dependent change destroys the portability of
the code, I would like better a statement whose spirit is that by default a
macromodule is the same as a module, but an implementation may add a special
mode which may be switched on or off which treats macromodules differently.
Shalom
On Tue, 11 Feb 2003 brad.pierce@synopsys.com wrote:
> Date: Tue, 11 Feb 2003 19:00:23 -0800
> From: brad.pierce@synopsys.com
> To: etf-bugs@boyd.com
> Subject: errata/189: PROPOSAL - 12.1, macromodule needs clarification
>
> Precedence: bulk
>
> In 12.1 --
>
> REPLACE --
>
> "The keyword 'macromodule' can be used interchangeably with
> the keyword 'module' to define a module. An implementation
> can choose to treat module definitions beginning with
> macromodule keyword differently."
>
> WITH
>
> "The keyword 'macromodule' can be used in place of the
> keyword 'module' to declare a module. An implementation
> may choose to inline the contents of modules that are
> declared with the 'macromodule' keyword within the
> modules that instantiate them. In such cases, the
> naming convention used to reference elements within
> instantiated macromodules may differ from that used
> to reference elements within instantiated modules."
>
>
> http://boydtechinc.com/cgi-bin/issueproposal.pl?cmd=view&pr=189
>
This archive was generated by hypermail 2.1.4
: Sat Feb 15 2003 - 09:40:28 PST
and
sponsored by Boyd Technology, Inc.