Re: Ship a revised Verilog-2001

From: Shalom.Bresticker@motorola.com
Date: Sun Mar 02 2003 - 12:23:55 PST

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    I hate to say, "I told you so," but I have been advocating this position for a
    long time ...

    Shalom

    On Wed, 26 Feb 2003, Stuart Sutherland wrote:

    > In a hallway conversation at DVCon, a valid concern from an EDA vendor was
    > brought up. The concern is that they need a version of the 1364-2001 LRM
    > that reflects all of the ETF work has done. This vendor is concerned that
    > if the 1364 committee begins to add enhancements to 1364, they will have to
    > wait much longer for "clean" Verilog-2001 LRM. They are equally concerned
    > that some EDA vendors will use the current 1364-2001 LRM--with all its
    > formatting and other errata--as an excuse to postpone implementing
    > Verilog-2001.
    >
    > I agree with this vendor. The current LRM being distributed by the IEEE is
    > too difficult to use due to the many formatting errata the IEEE added to
    > the document. The many additional errata/clarifications that have been
    > approved by the ETF make the current LRM even less usable. We should have
    > a clean, up-to-date LRM as a baseline for when we begin to add enhancements.

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