Re: errata/292: 12.3.3 : net declaration before port declaration

From: Steven Sharp (sharp@cadence.com)
Date: Tue Mar 04 2003 - 15:00:02 PST

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    The following reply was made to PR errata/292; it has been noted by GNATS.

    From: Steven Sharp <sharp@cadence.com>
    To: etf-bugs@boyd.com, Brad.Pierce@synopsys.com
    Cc:
    Subject: Re: errata/292: 12.3.3 : net declaration before port declaration
    Date: Tue, 4 Mar 2003 17:58:51 -0500 (EST)

    >>Number: 292
    >>Category: errata
    >>Originator: "Brad Pierce" <Brad.Pierce@synopsys.com>
    >>Environment:
    >>Description:
    >
    >Is the following example legal?
    >
    > module m(x);
    > wire x;
    > input x;
    > endmodule
     
     Not according to Verilog-XL.
     
     Steven Sharp
     sharp@cadence.com
     

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